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    I n k a r p

    FlexAFM

    Performance without compromise

    The DriveAFM is Nanosurf’s novel flagship AFM platform: a tip-scanning atomic force microscope (AFM) that combines, for the first time, several capabilities in one instrument to enable novel measurements in materials and life sciences. The DriveAFM overcomes drawbacks of other tip-scanning instruments and provides atomic resolution together with fast scanning, fast force spectroscopy, and large scan sizes up to 100 µm. Thanks to Nanosurf’s innovations in optical beam path engineering and scanner design, the Drive scan head features photothermal actuation and full motorization for superior research performance and is easy to use for researchers at all levels of experience.

    • CleanDrive: stable excitation in air and liquid
    • Ultra-low noise
    • Direct drive: high-resolution imaging and large scan area
    • Fully motorized system: full control via software
    • Technical Data
    Scan head  
    Scan size typ. typ. 100 µm x 100 µm x 20 µm
    min. 95 µm x 95 µm x 18 µm
    Read-out light source 840 nm low-coherence SLD
    CleanDrive light source 785 nm laser
    Photodetector bandwidth ≥8 MHz
    Standard / maximum sample size 100 mm / 150 mm
    Z-height noise dynamic <30 pm (RMS)
    Z-height noise static <30 pm (RMS)
    DC detector noise* <5 pm (RMS, 0.1 Hz – 10 kHz)
    AC detector noise* <25 fm/√(Hz) above 100 kHz
    Approach 10 mm motorized, parallel
    (*) measured with a USC-F1.2-k7.3 cantilever
    CX Controller specifications  
    High resolution outputs (DAC) 12x 28 bit, 1 MHz/sampling; thereof 4x user DAC (optional)
    Fast outputs (DAC) 4x 16 bit, 100 MHz/sampling; thereof 1x user DAC (optional)
    High resolution inputs (ADC) 12x 20 bit, 1 MHz/sampling; thereof 4x user ADC (optional)
    Fast inputs (ADC) 3x 16 bit, 100 MHz/sampling; thereof 1x user ADC (optional)
    Signal analyzers 2 signal analyzer function blocks that can be configured as dual channel lock-in
    FPGA module and embedded processor System-on-chip module with low-latency FPGA signal processing at 100MHz and dual-core ARM processor, 2GB RAM, 1.5GHz clock
    Scan control 28-bit X/Y/Z-DAC
    Detector inputs Deflection/lateral signals each 20 bit
    Digital sync, Spike-Guard 2-bit line/frame sync out 5 V/TTL galvanically isolated, Spike-Guard input
    Clock sync 10MHz/3V clock input to synchronize data acquisition and processing
    Communication to PC Gigabit Ethernet, galvanically isolated

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